Digital processor and viterbi decoder having shared memory

Details Digital processor and viterbi decoder having shared memory Digital processor and viterbi decoder having shared memory

1993-11-16

1995-07-11

Envall, Jr., Roy N.

Excavating

375340, G06F 1110

Patent

active

054328047

ABSTRACT:
An integrated circuit includes a digital signal processor (DSP) and an error correction co-processor (ECCP) that implements a Viterbi decoding function. The DSP and ECCP share a block of multi-port memory, typically by bus multiplexing a dual-port RAM. When the ECCP possesses the RAM, it inhibits the DSP from accessing that block of the RAM by asserting an EBUSY flag. This technique conserves and optimizes the RAM usage, allowing the DSP and ECCP to advantageously be formed on the same integrated circuit chip.

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Ellard, G. S. and J. P. Sweeney, AT&T Cellular Applications Engineering, DSP Applications, Algorithm Implementation Examples for Digital Cellular Communication, Mar. 1993, pp. 53-65.

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