Digital processing circuit having a multiplication function

Details Digital processing circuit having a multiplication function Digital processing circuit having a multiplication function

1982-02-25

1985-10-08

Smith, Jerry

Boots, shoes, and leggings

364757, G06F 754

Patent

active

045464464

ABSTRACT:
In a Booth's algorithm multiplication circuit, a multiplicand is set in a multiplication register and a multiplier is set in a multiplier shift-register. Consecutive bits of the multiplier are applied to a Booth's decoder to produce coefficients, and the multiplicand and coefficient are multiplied by each other to produce a partial product. Partial products are produced for every three consecutive bits of the multiplier, and the obtained partial products are added to the sum of previously obtained partial products. After all the partial products are added together, the resultant sum is derived from the adder or from the feed-back path of the output from the adder.

REFERENCES:
patent: 3878985 (1975-04-01), Ghest et al.
patent: 4027147 (1977-05-01), Majos et al.
patent: 4142242 (1979-02-01), Duvochel et al.
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4228518 (1980-10-01), Chamberlin
patent: 4405992 (1983-09-01), Blau et al.
Gerberich, F. G., "Multiplier/Divider Hardware Design Accelerates Microprocessor Throughput", Computer Design/Jun. 1979.

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