Digital processing circuit comprising test registers

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348721, H04N 132

Patent

active

056361424

ABSTRACT:
The invention relates to a digital processing circuit comprising a host interface (7) which provides access from the processing circuit's bus (6) to an external data processing system (8). The processing circuit is broken down into blocks (1, 2, 3) with test registers (4, 5) interposed between an upstream block and a downstream block. The test registers (4, 5) are connected to the bus (6) and identified by an address allowing data to be sent to them or read from them.

REFERENCES:
patent: 4701921 (1987-10-01), Powell et al.
patent: 4991019 (1991-02-01), Enami et al.
patent: 5218688 (1993-06-01), Nishida
patent: 5325092 (1994-06-01), Allen et al.

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