Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-06-16
2002-06-25
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06411975
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to digital processing in general and in particular the implementation of functions such as maximum and minimum detection and storage.
The conventional circuitry and method for implementing maximum and minimum type instructions is illustrated in
FIG. 1
of the accompanying drawings. A source operand is applied to one input (
10
) of an arithmetic logic unit (
14
) and an existing destination operand is applied to the other input (
12
) of the arithmetic logic unit. The destination operand is stored in a destination register
16
. Subtraction of the destination operand from the source operand is performed by the arithmetic logic unit. The difference and the generated status are used by a control logic unit (
18
) which determines whether the loading of the source operand in to the destination register (
16
) should be enabled. The control logic unit (
18
) can determine that the destination operand is greater than the source operand when the result of the subtraction, the difference, is negative. This, however, is dependent upon there having been no overflow during the subtraction operation. If overflow has occurred then it is necessary to assess the most significant bits of the operands, as input in to the arithmetic logic unit, in order to determine which operand is greater. Thus, a vital part of the conventional circuit is the overflow-flag generation unit (
20
). Detection of the overflow condition is an integral part of conventional digital processors and forms part of the overall processor status generation hardware.
The conventional method and circuit, as illustrated in
FIG. 1
, is slowed by the need to detect whether or not overflow has occurred during subtraction. Additionally, it is common for conventional processors also to detect “greater-than-or-equals-to” and “less-than-or-equals-to” conditions rather than simple maximum or minimum conditions. This requires additional circuit elements, which further adds to the delay introduced by the overall circuit. Such delays can have a significant impact on the operation of a well balanced high performance processor.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a digital processor comprising an arithmetic unit, a control logic unit and a destination storage unit, the processor being capable of implementing at least one of a maximum and a minimum instruction between a source operand and a destination operand; the arithmetic unit having respective inputs for receiving the source and destination operands and an output for outputting the result of an arithmetic operation performed using the source and destination operands; the control logic unit being connected between the arithmetic unit output and the destination storage unit and operatively controlling storage of data in the destination storage unit, wherein the control logic unit is operatively controlled by the sign of the source operand, the sign of the destination operand and the sign of the result.
According to a second aspect of the present invention there is provided a method of digital processing including implementing at least one of a maximum and a minimum instruction between a source operand and a destination operand comprising performing an arithmetic operation using the source and destination operands to generate a result; and controlling storage of data in the destination storage means in accordance with the sign of the source operand, the sign of the destination operand and the sign of the said result.
REFERENCES:
patent: 4774688 (1988-09-01), Kobayashi et al.
patent: 4967349 (1990-10-01), Kodama et al.
patent: 5508951 (1996-04-01), Ishikawa
patent: 5515306 (1996-05-01), Blaner et al.
patent: 5524251 (1996-06-01), Urasaki
patent: 5715186 (1998-02-01), Curtet
patent: 5726923 (1998-03-01), Okumura et al.
LSI Logic Corporation
Mai Tan V.
Westman Champlin & Kelly
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