Digital PLL using phase and frequency error calculating circuits

Details Digital PLL using phase and frequency error calculating circuits Digital PLL using phase and frequency error calculating circuits

1997-09-26

1998-11-24

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 14, 331 18, 331 25, H03L 7087

Patent

active

058413235

ABSTRACT:
An A/D converter performs sampling of a reproduced signal from a reading device in synchronism with a clock signal from a PLL circuit and outputs the sampled value to a binary circuit and a phase comparator. The phase comparator detects a change from a positive sampled value to a negative one or from the negative sampled value to a positive one (zero-cross) and outputs a phase error signal corresponding to the zero-cross to a frequency comparator. The frequency comparator outputs a frequency error sensed in reference to a variation of the phase error signal to a switch through a low pass filter. The switch outputs the frequency error to an adder only when the PLL is not in a lock state. The adder outputs a sum of the frequency error and the phase error to a VCO through a loop filter. The VCO generates the clock signal with a frequency corresponding to the sum and supplies it to the A/D converter.

REFERENCES:
patent: 4069462 (1978-01-01), Dunn
patent: 5416809 (1995-05-01), Masuda et al.

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