Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Patent
1996-11-01
1998-05-05
Grimm, Siegfried H.
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
331 27, 327 7, 327159, H03L 7085, H03L 718
Patent
active
057480435
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to frequency synthesizers and, in particular, to digital frequency synthesizers using a phase locked loop (PLL) to produce a signal having a frequency f.sub.s which is a rational fraction of a reference frequency f.sub.r according to the relationship: in variety of applications including, but not limited to, telecommunications systems and radio measurement equipment.
2. State of the Art
A known digital frequency synthesizer is disclosed in U.S. Pat. No. 3,913,028 to Bosselaers. This known synthesizer uses an oscillator, as part of a PLL, controlled by a signal from an arithmetic unit, combined with a digital-to-analog converter (DAC), and a low-pass filter. This architecture permits a high speed of operation and high resolution in frequency, but lacks the spectral purity of output signal required in many cases. Modern telecommunications and radio measurement equipment require frequency synthesizers which have a high spectral purity of output in addition to a high speed of operation and high resolution in frequency.
A series of advanced frequency synthesizers providing a signal of better spectral purity are disclosed in Kozlov, V. I., Frequency Synthesizers Based on Using Accumulators, Electrosvyaz, 1988, No.2, pp. 53-56 (the English translation of this magazine is published in the U.S.A. by Scripta Publishing Company, under the title, "Telecommunications and Radio Engineering"). These synthesizers are based on a digital phase demodulation of two pulse trains, reference and controllable, having different frequencies, and utilize accumulators, an RS flip-flop and a DAC. The result of phase comparison of these two pulse trains is fed from the DAC, via a low-pass filter, to a controllable oscillator whose output is adjusted by the PLL to whatever relationship with the reference frequency is required. The desired signal frequency is determined by code-setting of the inputs to the accumulators. The improvement in signal spectral purity, gained in this way, is not enough, however. The signal spectrum still contains some discrete components, which may be called fractional spurs, because the frequencies of the reference signal and output pulse trains are not in integer relationship with each other. The level of these fractional spurs depends on the accuracy of the DAC which, in turn, is limited by the current technological state of the art. For example, using an 8-bit DAC, the level of fractional spurs is typically no less than -48 dBc. In many cases, this level of fractional spurs is unacceptable. The problem of minimizing these spurs is still a prime concern in the design of frequency synthesizers.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a frequency synthesizer utilizing a DAC where the spectral purity of the output signal is improved over the current art for a DAC of given accuracy.
It is also an object of the invention to provide a frequency synthesizer which has a high speed of operation and a high resolution in frequency.
In accord with these objects which will be discussed in detail below, the synthesizer of the present invention includes a DAC with its analog output coupled to a low-pass filter which, in turn, is coupled to a controlled oscillator (VCO) whose output is the output of the synthesizer. A frequency to be synthesized is selected by a binary number which is input to a first accumulator. The outputs of the first accumulator are fed through a phase splitter having K outputs (where K=2.sup.k and k is the number of the accumulator's bits) which are each coupled to the S input of a respective RS flip-flop. The output of each of the flip-flops is coupled to first equally weighted inputs of the DAC. A reference frequency serves as the clock input for the accumulator and the phase splitter. The output signal of the VCO is coupled to the clock input of a pulse distributor having w outputs each of which is coupled to the R input of a respective number (K/w) of the RS flip-flops (where K/w
REFERENCES:
patent: 3913028 (1975-10-01), Bosselaers
patent: 4144579 (1979-03-01), Nossen et al.
patent: 5008629 (1991-04-01), Ohba et al.
patent: 5019785 (1991-05-01), Fognini et al.
"Frequency Synthesizer on the Base of Summing Accumulators", Elektrocvyaz, Issue #2, 1988, pp. 53-56.
Gallagher Thomas A.
Gordon David P.
Grimm Siegfried H.
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