Digital PLL decoder

Details Digital PLL decoder Digital PLL decoder

1983-11-09

1986-04-22

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

328 63, 328 72, 329122, H03D 318

Patent

active

045846952

ABSTRACT:
A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.

REFERENCES:
patent: 3956623 (1976-05-01), Clark et al.
patent: 4280099 (1981-07-01), Rattlingourd
patent: 4302845 (1981-11-01), McClaughry et al.
patent: 4330863 (1982-05-01), Wright
patent: 4380081 (1983-04-01), Di Tria
patent: 4400817 (1983-08-01), Sumner
patent: 4414676 (1983-11-01), Kraul et al.

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