Digital PLL circuit operable in short burst interval

Details Digital PLL circuit operable in short burst interval Digital PLL circuit operable in short burst interval

2005-02-15

2005-02-15

Ha, Dac V. (Department: 2734)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S375000, C375S376000, C370S516000, C327S146000, C327S152000, C327S159000, C327S163000

Reexamination Certificate

active

06856658

ABSTRACT:
A digital PLL (phase locked loop) circuit includes a sampling circuit, a plurality of internal circuits and an output switching circuit. The sampling circuit samples a burst data signal in response to a multi-phase clock signal to produce N (N is a positive integer larger than one) sampled data signals. The multi-phase clock signal includes N clock signals, each of which has substantially the same frequency as the data signal and which have phases different by a predetermined component from one after another. Each of the plurality of internal circuits is selected in response to a first selection signal, and outputs a set of a selected one of the N clock signals and an identified data signal from the N sampled data signals, which corresponds to the selected clock signal, in response to the selected clock signal, when the internal circuit is selected. The output switching circuit selects the set corresponding to the selected internal circuit from among the sets from the plurality of internal circuits based on a second selection signal.

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