Digital PLL circuit having reduced lead-in time

Details Digital PLL circuit having reduced lead-in time Digital PLL circuit having reduced lead-in time

1989-09-27

1991-04-30

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307262, H03K 500, H03K 513, H03K 522

Patent

active

050121987

ABSTRACT:
A digital PLL circuit to output a clock signal phase-synchronized with an input signal comprises a divider outputting the clock signal and a signal initiation pulse generator generating a signal to set the divider to a predetermined state depending on the input signal initiation. The maximum lead-in time is reduced to 1
in comparison with prior art, and therefore the circuit is very suitable for use in the receiving part of a device which receives a burst data signal.

REFERENCES:
patent: 4841167 (1989-06-01), Saegusa
patent: 4849703 (1989-07-01), Easley et al.
patent: 4893087 (1990-01-01), Davis

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