Digital PLL circuit having a look-up table and method thereof

Details Digital PLL circuit having a look-up table and method thereof Digital PLL circuit having a look-up table and method thereof

2000-04-26

2002-05-21

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S018000, C331S025000, C327S156000

Reexamination Certificate

active

06392496

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase locked loop (PLL), and more particularly, to a digital PLL circuit operable at a high speed.
2. Background of the Related Art
Generally, a digital processing PLL (DP-PLL) adopted in a communication system is used for synchronizing a network synchronization clock and a system clock. Having a principle similar to a general analog PLL, it is widely called DP-PLL because it uses a digital processor for controlling the PLL.
FIG. 1
is a schematic block diagram of a general digital processing PLL in accordance with the background art. As shown in
FIG. 1
, the general digital processing PLL includes a phase-detector
1
for outputting a phase difference value between a reference clock (input CLK) inputted from a first terminal and a comparative clock (divided CLK) inputted after being fedback by a second terminal as a digital value. A dual-port memory
2
stores the phase difference value of a predetermined unit outputted from the phase detector
1
. A central processing unit (CPU)
3
reads the data stored in the dual-port memory
2
, block by block, and computes an average phase difference value. A digital to analog converter (DAC)
4
receives the average phase difference value from the CPU
3
and converts the difference value to a corresponding analog signal or voltage. A voltage controlled oscillator (VCO)
5
generates a predetermined output clock signal (VCO CLK) based on the voltage value inputted from the DAC
4
. Finally, the general DP-PLL shown in
FIG. 1
includes a divider
6
for dividing the output signal (VCO CLK) of the VCO
5
into a clock signal (divided CLK) of a predetermined frequency.
The operation of the general digital processing PLL in accordance with the background art will now be explained with reference to
FIGS. 2A and 2B
, which show waveforms of each clock signal of the DP-PLL shown in FIG.
1
. In this example of the background art, a reference clock (input CLK) inputted to the phase detector
1
is 4 KHz, an output clock (VCO CLK) outputted from the VCO
5
is 25.92 MHz, and a comparative clock (divided CLK) divided by the divider
6
is 8 KHz.
As shown in
FIG. 2A
, the phase detector
1
counts the output clock VCO CLK (25.92 MHz) every 4 KHz (125 us) for the phase difference between the input CLK (4 KHz) and the divided CLK (8 KHz) and outputs the counted values (X
N
S
, X
N
S+1
. . . to the dual port memory
2
. As shown in
FIG. 2B
, when the phase detector counts the counted values for one block cycle of k input clock cycles (k×125 us, for X
N
1
, . . . X
N
k
where k is a position integer), the CPU
3
reads the phase difference values corresponding to the block cycle, and computes an average value of the k phase difference values.
Subsequently, the average phase difference value computed by the CPU
3
is inputted to the DAC
4
and converted to a corresponding analog value. The analog value becomes a control voltage value for controlling the VCO
5
, which generates a clock signal (VCO CLK) having a predetermined frequency (e.g., 25.92 MHz) based on the control voltage. The divider
6
divides the VCO CLK into a divided CLK signal of 8 KHz and outputs the divided CLK signal to the phase detector
1
.
However, the digital processor PLL of the background art has a problem in that a considerable time delay occurs in order for the CPU
3
to read the data for one block cycle from the dual port memory
2
and average the data. Since computing several arithmetic operations requires excess system time, a desired operation can not be performed within a short period of time, such as a few ms, and thereby fails to meet the international standards (ITU-T G.813) limiting the control speed to a specified time.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a digital PLL circuit.
Another object of the present invention is to compute phase differences between an input reference clock signal and an output clock signal.
Another object of the present invention is to compute feedback from a VCO.
Another object of the present invention is to reduce an overloading of a communication system.
Another object of the present invention is to perform a signal processing at a high speed.
The present invention can be achieved, as a whole or in part, by a digital PLL circuit, including a phase difference computing circuit that compares a first clock signal and a second clock signal fedback from a voltage controlled oscillator (VCO), and computes a phase difference value for one the unit of at least one first clock signal cycle and at least one second clock signal cycle, a control unit for reading a phase difference correcting value corresponding to the phase difference value from a predetermined look-up table and synchronizing the output clock signal of the VCO with the first clock signal, and a memory unit for storing the look-up table.
The present invention can also be achieved, as a whole or in part, by a method for controlling a phasing of a digital PLL circuit, including comparing a first clock signal input from a reference clock generator and a second clock signal fedback from a voltage controlled oscillator (VCO computing a phase difference value between the first and second block signals for a time unit, reading a phase difference correcting value corresponding to the phase difference value, and synchronizing the second clock signal of the VCO with the first clock signal.
The present invention can also be achieved, as a whole or in part, by a digital PLL circuit, including a counter that receives a first clock signal inputted from a reference clock generator and a second clock signal fedback from a voltage controlled oscillator (VCO) and counting the number of cycles of the second clock signal from the time when the first clock signal and the second clock signal are synchronous as a counter value, a phase detector that detects the counter value of the second clock signal for every cycle of the first clock signal, an adder that adds the counter values output from the phase detector to compute a phase difference value for one time unit, a buffer that temporarily stores the added counter value while the adder adds the counter values output from the phase detector for a next time unit, a memory unit that stores a pre-computed phase difference correction value corresponding to the phase difference value in a look-up table, a central processing unit (CPU) that receives the stored added counter output from the buffer for one time unit and reads a corresponding phase difference correcting value from the memory unit, and a digital to analog converter (DAC) for outputting an analog voltage value for driving the VCO in accordance with the corresponding phase difference correcting value; wherein the VCO generates the second clock signal synchronized with the first clock signal according to the analog voltage value output from the DAC.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 5036294 (1991-07-01), McCaslin
patent: 5373255 (1994-12-01), Bray et al.
patent: 5576664 (1996-11-01), Herold et al.

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