Television – Synchronization – Automatic phase or frequency control
Reexamination Certificate
1997-10-16
2001-01-16
Kostak, Victor R. (Department: 2711)
Television
Synchronization
Automatic phase or frequency control
C348S549000, C348S844000
Reexamination Certificate
active
06175385
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital PLL (phase locked loop) circuit and an MPEG (Moving Picture Experts Group) decoder, and more particularly, to a digital PLL circuit for an MPEG stream.
2. Description of the Related Art
The techniques standardized by MPEG for compressing dynamic images are widely used. An MPEG system stream compressed according to MPEG-2:ISO-13818-1 contains audio and video streams. The audio and video streams require synchronized output timing to realize harmony in reproduced sounds and images and avoid inconveniences that a person in the screen moves his mouth without uttering a sound and that a bang occurs sometime after a door is closed on the screen.
Compressed audio and video information transmitted in an MPEG transmission stream to an MPEG decoder is temporarily stored in a memory of the decoder until it is needed to reproduce original sounds and images. The transmission stream is usually provided at a fixed speed, and therefore, the memory will be full of information if the information reproducing speed is slow. This results in abandoning part of the received information. This must be avoided. On the other hand, if the information reproducing speed is too fast, the memory will be empty to stop sounds and images being provided for the viewer. This also must be avoided. It is necessary, therefore, to adjust the information transmission and reproducing speeds to each other.
Namely, the transmitter must provide the receiver with a proper amount of information so that the memory of the receiver may cause no overflow or underflow and so that the receiver may reproduce sounds and images in harmony.
To improve a compression ratio of video information, MPEG sometimes transmits only the difference between a preceding image and a current image. In this case, the compression ratio differs depending on images. For example, a still image involves little information to be transmitted in a unit period, while a moving image involves a lot of information to be transmitted in the same period.
To transmit such video information having different compression ratios, a technique of varying transmission capacity depending on compression ratios is not popular. Instead, a fixed capacity transmission is widely employed. For example, a broadcasting system transmits a digital stream by assigning a fixed transmission band to a given channel and by employing a fixed transmission bit rate and a fixed frame rate (30 frames per second).
Since the amount of information to be transmitted differs depending on compression ratios, the difference between the fixed transmission rate and the varying information amount must be absorbed. For this purpose, the international standards specify the capacity of a receiver memory (a VBV buffer) to temporarily store compressed information transmitted at the fixed rate. A processor of the receiver reads the information out of the memory, expands the same, and displays original images according to the expanded information.
If information is transmitted at a high compression ratio, the memory accumulates more information than an amount of information read out therefrom. If the compression ratio is low, information accumulated in the memory is read out therefrom to reproduce images without deteriorating the quality of the images. The international standards specify a way of compressing video and audio data without causing an overflow or underflow in the memory.
To reproduce sounds and images in harmony without an overflow or underflow in the memory, MPEG stipulates that a transmitter must send a program clock reference (PCR) that indicates a current time, which the transmitter assumes and a presentation time stamp (PTS), which indicates a time of which the transmitter expects images and sounds to be reproduced. Namely, the transmitter sets the PCR and instructs a receiver when images and sounds, transmitted thereto must be reproduced. By simply following the instructions, the receiver is able to provide a viewer with matching sounds and images without causing an overflow or underflow in a VBV buffer of the receiver. Namely, the transmitter's responsibility to prevent an overflow or underflow in the VBV buffer of a receiver.
MPEG specifies that PCR must be sent at intervals of every 0.1 seconds or shorter and PTS at intervals of every 0.7 seconds or shorter. On the other hand, the receiver generates its own internal reference clock signal based on PCR with the use of an oscillator and a PLL circuit that controls the oscillator. The frequency of the internal clock signal must be 27 MHz. Namely, the receiver drives, for example, a video signal processor according to the 27-MHz internal clock signal that is generated based on PCR provided by the transmitter at intervals of 0.1 seconds.
A PLL circuit installed in an MPEG decoder of a receiver usually consists of a DA (digital-to-analog) converter and a VCO (voltage controlled oscillator). These DA converter and VCO are expensive components and increase the cost of the MPEG decoder.
This and other problems of the conventional PLL circuit and MPEG decoder will be explained later with reference to drawings.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an inexpensive digital PLL circuit that employs no DA converter or VCO. Another object of the present invention is to provide an inexpensive MPEG decoder employing such a PLL circuit.
According to the present invention, there is provided a digital PLL circuit that employs a fixed-frequency output signal from a fixed-frequency oscillator, to provide a signal synchronized with an external reference signal, comprising a counting unit for counting clock periods of the fixed-frequency output signal and an adjusting unit for incrementing or decrementing a value counted by the counting unit a predetermined number of times in a predetermined period according to a deviation of the fixed-frequency output signal from the reference signal.
The counting unit may count clock periods of a signal whose frequency is n times the frequency of the fixed-frequency output signal, where n is a positive integer. The digital PLL circuit may be applied to an MPEG decoder, the reference signal may be a program clock reference signal in an MPEG stream, and the output signal of the digital PLL circuit may be used as a clock signal for synchronizing a stream receiver of the MPEG decoder with the program clock reference signal.
The digital PLL circuit may be used to decode and reproduce MPEG audio information. The digital PLL circuit may be used to decode and reproduce MPEG video information.
The digital PLL circuit may adjust a phase of a predetermined signal when converting the decoded MPEG video information into television signals. The decoded MPEG video information may be digitally converted into television signals by an NTSC encoder according to the reference signal or a clock signal synchronized with the reference signal, and the digital PLL circuit may reversely adjust, according to phase information, a phase of a color sub-carrier used by the NTSC encoder when carrying out a conversion, the phase information being for correcting a hue error caused by an adjustment made by the adjusting unit.
The digital PLL circuit may correct a value counted by a counter that controls an overall timing of an output circuit operating on the reference signal, thereby synchronizing the counter with the reference signal. A value counted by the counter that controls the overall timing of the output circuit operating on the reference signal may be incremented or decremented once or a plurality of times by a predetermined value in a predetermined period, to change the overall timing of the output circuit and synchronize the same with the reference signal. The predetermined value and the number of increments or decrements in the predetermined period may be adjustable.
An increment or a decrement in the value counted by the counter may be carried out in one or a plurality of time bands in a blanking period after image
Kohiyama Kiyoshi
Shirai Hideaki
Tahira Takahiko
Fujitsu Limited
Kostak Victor R.
Staas & Halsey , LLP
LandOfFree
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