Digital PLL circuit

Details Digital PLL circuit Digital PLL circuit

1995-05-15

1997-08-26

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327160, 327156, 327150, 327147, 327151, 331 1A, 375376, H03K 513

Patent

active

056614250

ABSTRACT:
A phase control circuit adjusts the width of a PLL clock signal so that a PLL clock signal generated from a master clock signal MCK is in synchronization with an EFM signal. A velocity detector detects offset in velocity by counting a pulse width of an EFM signal with a master clock signal MCK. The phase control circuit alters the pulse width of a PLL clock signal according to the detected offset in velocity to alter the average frequency of a PLL clock signal in proportion to offset of the rotational speed.

REFERENCES:
patent: 4019153 (1977-04-01), Cox et al.
patent: 4538119 (1985-08-01), Ashida
patent: 4827225 (1989-05-01), Lee
patent: 5111151 (1992-05-01), Ii

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