Digital PLL circuit

Details Digital PLL circuit Digital PLL circuit

1993-02-02

1994-06-07

Dolinar, Andrew M.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 14, 331 17, 331 25, H03L 7091

Patent

active

053193210

ABSTRACT:
A digital PLL circuit capable of stabilizing a phase comparison operation to largely reduce a jitter of an output signal, including a peak detection circuit for detecting a peak of an input signal level, a two-points sampling circuit for sampling two data points determined at a predetermined time interval in the peak to output two sample values, an inclination calculation circuit for calculating an inclination value from the two sample values, and a discrimination circuit for discriminating whether the inclination value is zero or either a positive or negative value to output a control signal for a VCO depending on the discrimination result.

REFERENCES:
patent: 3602834 (1971-08-01), McAuliffe
patent: 3840821 (1974-10-01), Conway

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