Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-08-23
2004-03-16
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C327S065000, C341S162000, C341S169000, C348S301000
Reexamination Certificate
active
06707410
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a digital pixel sensor architecture. More specifically, a digital pixel architecture which incorporates a dynamic comparator having reduced sensitivity to threshold voltage mismatches in its input transistors.
BACKGROUND OF THE INVENTION
A conventional digital pixel sensor
100
architecture is illustrated in FIG.
1
. The conventional digital pixel sensor
100
includes a photoconversion element, such as a photodiode, for converting optical energy into an analog electrical signal. The electrical signal is supplied to an analog-to-digital converter (ADC), which converts the analog electrical signal into a digital signal. The conventional digital pixel sensor
100
therefore differs from several other pixel sensor architectures, such as CMOS active pixel sensors (APS), because the conventional digital pixel sensor performs local analog-to-digital conversion (i.e., digitization at each pixel) instead of global analog-to-digital conversion (i.e., digitization at a common location outside the pixel).
The conventional digital pixel sensor
100
architecture has several advantages over pixel architectures which perform global analog-to-digital conversion. For example, the analog signal generated by the photodiode
101
is susceptible to substrate noise and column fixed pattern noise. A local digitization architecture minimizes these susceptibilities. Additionally, the conventional digital pixel sensor
100
architecture is capable of operating at a higher speed, since an entire array of pixels may be digitized at once. In contrast, each pixel of an active pixel sensor array must be sequentially digitized. Thus, the gap in speed between sensor architectures such as the digital pixel sensor
100
and an active pixel sensor increases with resolution.
The conventional digital pixel sensor
100
architecture, however, is problematic because the increased circuitry, i.e., the local analog-to-digital converter and the local memory increase circuit complexity which reduces fill factor, i.e., less of the pixel circuitry is devoted to converting light into electrical signals. Additionally, the location of a memory within the pixel makes it difficult to access the information stored in the memory. Accordingly, there is a need and desire for a pixel architecture which is fast, has good fill factor, and minimizes substrate and fixed pattern noise.
SUMMARY OF THE INVENTION
The present invention is directed to a digital pixel sensor (DPS) architecture which incorporates a new comparator and divides the analog-to-digital conversion circuitry between each pixel and a column processing circuit of the pixel array. The digital conversions are performed one row at a time, instead of for the entire array at once. The row-by-row digitization does not degrade the speed of the DPS architecture since the speed of an imaging system is typically limited by a chip's off-chip data output rate. The row-by-row digitization is also advantageous because the limited number of simultaneous conversions provides superior noise immunity. The digitized values are stored in a separate frame memory independent of the pixel circuitry. The DPS architecture of the present invention has a better fill factor because each pixel no longer includes its own frame memory and analog-to-digital converter. At the same time, the DPS architecture of the present invention preserves the superior noise and speed characteristics associated with digital pixel systems. The comparator is preferably of a new design which shares the low power characteristics of dynamic comparators, but which is less sensitive to mismatching of the threshold voltages of its input transistors.
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Kotani et al., KOJI, “Cmos Charge-Transfer Preamplifier for Offset-Fluctuation Cancellation in Low-Power A/D Converters”, IEEE Journal of Solid State Circuits, vol. 33, No. 5, May 1998.
Weste et al., Neil H.E., “Principles of CMOS VLSI Design A Systems Perspective”, Chapter 8, pp. 520-526., Dec. 2000, © 2001 Addison-Wesley Publishing Inc.
Phase I SBIR Final Report: Oct. 8, 1998, “Photobit”.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Williams Howard L.
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