Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-12-09
2001-10-30
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S149000, C327S141000
Reexamination Certificate
active
06310498
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to phase selection of a clock signal and, in particular, to apparatus and methods for producing different phases of a clock signal and for selecting certain of these clock signals for operating a system with reduced jitter.
In many systems, such as in digital clock recovery systems and frequency synthesis systems, clocking (or “timing”) signals are generated for “retiming” incoming data and/or performing needed timing/clocking operations. By way of example, in a digital clock recovery system, a basic clock signal of given frequency is generated together with a number of different clock signals of like frequency but with different phases, e.g., the different clock signals may be generated by applying the basic clock signal to analog and/or digital delay networks. Then, in the course of operating the system different ones of the clock signals are compared to the phase and frequency of an incoming data stream and certain ones of the clock signals are selectively switched into use by the system for performing data recovery. However, when a clock signal of one phase is switched into the system to replace a clock signal of a different phase there is a fixed, discrete, jump in the phase (timing) of the clock signal being used, even though the frequency is the same. The “jumping” back and forth in the phase of the clocking signal is problematic in that it introduces a certain discrete amount of jitter in the clocking/timing signals generated by the system and used therein.
The nature of the problem present in prior art systems may be better explained with reference to the prior art clock recovery circuit shown in of
FIG. 1
which includes a clock generation system for producing a clock signal with a predetermined number of phases. The clock generation circuit includes a reference clock signal (fref) applied to the input of a voltage controlled delay line (VCDL)
12
which is shown to include 4 inverters (I
1
,I
2
, I
3
,I
4
) connected in cascade between an input terminal
11
to which is applied fref and an output terminal
13
. The signal fref and the output of VCDL
12
are applied to a phase detector
14
which produces an output which controls a charge pump circuit
16
whose output is supplied to a filter
18
whose output voltage controls the delay in (and of) the stages of VCDL
12
. Consequently each one of the inverters in VCDL
12
produces a differently phased clock (i.e., &phgr;
1
, &phgr;
2
, &phgr;
3
, &phgr;
4
) but with all the clock signals having the same frequency.
The four output clocks (&phgr;
1
, &phgr;
2
, &phgr;
3
, &phgr;
4
) of VCDL
12
are supplied to a multiplexer
20
, which in response to a control signal (CTLS) selects one of the four VCDL generated clocks and couples it to the multiplexer output line
23
. In a clock recovery system an incoming data signal stream (DATA) applied to the system is compared to the phase of the clock signal on line
23
to ascertain that the data being received by the system has a particular frequency and phase. The clock signal on line
23
is applied to one input of a phase detector
22
having another input
24
to which is applied the incoming data signal stream (DATA) whose frequency and phase is to be ascertained. If there is a difference in phase between the incoming DATA on line
24
and the clock signal on line
23
an error signal is generated which is applied to a control circuit
25
which then produces an output signal (CTLS) on line
21
to cause multiplexer
20
to switch and select a different phase (i.e., a different one of the four clock signals being outputted by VCDL
12
) until there is a match between the frequency and phase of the clock signal and the frequency and phase of the incoming DATA. Note that the clock signal on line
23
and the incoming data signals are also applied to a data sampling flip-flop
26
at whose output is produced a “retimed” data signal which is then fed to an electronic system for processing. The clock signal on line
23
thus functions as a sampling clock which may also be termed the data “recovery” clock. Theoretically, to best sample the true value of incoming data bits, the sampling clock should sample the incoming data bits midway between the rising and falling edges of a data bit. When the sampling clock is subject to jitter the sampling clock may occur at or near the (rising or falling) edges of the incoming data bits resulting in a high number of erroneous sampling of the incoming data.
Thus, a problem with the circuit of
FIG. 1
is that when the control signal CTLS activates the multiplexer to select a different clock signal, the clock “recovery” signal at the output of the multiplexer, which is applied to line
23
, switches from one phase of the clocking signal to another phase of the clocking signal. This causes a discrete jump and resulting jitter, having a fixed minimum value, in the clocking and sampling signals supplied to the system and in the data to be processed by the system.
SUMMARY OF THE INVENTION
In systems embodying the invention a voltage responsive circuit, e.g., a voltage controlled oscillator (VCO) or a voltage controlled delay line (VCDL), is used to generate X different clock signals having the same frequency but different phases, where X is any integer greater than one. The different clock signals are multiplexed and the multiplexed output is compared to a reference frequency for producing a control voltage (VCTL) applied to the voltage responsive circuit.
In a particular embodiment of the invention the multiplexing of the different clock signals includes the application of the X different clock signals to the input port of a selection circuit which is responsive to a control signal for selecting a different one of the X clock signals and for supplying the selected clock signal at an output of the selection circuit. The selected clock signal is then compared to a reference frequency signal to produce the control voltage applied to the voltage responsive circuit.
In a particular embodiment of the invention, a designated one of the different clock signals generated by the voltage responsive circuit is compared with an incoming data signal stream for producing the control signal which is indicative of their phasal and frequency relationship. This control signal controls the selection of the different clock signals to be compared with the reference signal. Also, the designated one of the different clock signals, or any other ones of the X clock signals, may be used as a clock (“data”) recovery signal to sample the incoming data signal stream for producing “retimed” data signals ready for further data processing.
In accordance with the invention, the control voltage applied to the voltage responsive circuit (VCO or VCDL) is a gradually varying voltage although it is produced by selectively switching from a first clock signal having one phase to a second clock signal having another phase and by comparing the new switched-in clock signal with the reference signal. The gradually varying control voltage causes the phase and/or frequency of the X clock signals produced by the voltage responsive circuit to vary gradually. The use of any of these gradually varying X clock signals as a clock recovery signal reduces the jitter in the data signals transmitted for processing.
Thus, in circuits embodying the invention, the clock recovery signal is a designated one of the X clock signals which varies gradually from one value towards a second value. This is in contrast to the prior art scheme, discussed above, where the clock recovery signal is obtained by switching between different phases of the clock signals. This switching causes the clock recovery signal to switch quickly from one value to another value and results in jitter in the data signals transmitted for processing.
REFERENCES:
patent: 5389898 (1995-02-01), Etoshi et al.
patent: 5889436 (1999-03-01), Yeung et al.
Agere Systems Guardian Corp.
Le Dinh T.
Schanzer Henry I.
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