Digital phase meter circuit

Details Digital phase meter circuit Digital phase meter circuit

1986-12-11

1988-01-26

Levy, Stewart J.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Phase comparison

324 79D, 328133, 307514, G01R 2500

Patent

active

047219050

ABSTRACT:
To determine the phase difference between the edge of a pulse of a first clock signal and the edge of a pulse of a second clock signal with an integrable phase meter circuit, the second clock signal is fed through a frequency-divider circuit to the input of an unclocked delay line including m delay elements, and to a second register containing m cells, while the m cells of a first register are clocked by the first clock signal. The outputs of the kth register cells are compared in the kth XOR gate of a row of m XOR gates, so that, when the levels of these outputs are unlike, a logic 1 appears at the output of the kth gate. The phase is obtained at the n-bit output of a multiple adder adding the logic levels, the accuracy corresponding to m, which is preferably equal to 2.sup.n.

REFERENCES:
patent: 3984771 (1976-10-01), Nossen et al.
patent: 4025848 (1977-05-01), Delagrange
patent: 4144572 (1979-03-01), Starner et al.
patent: 4471299 (1984-09-01), Elmis

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