Digital phase locked loop with selectable normal or...

Details Digital phase locked loop with selectable normal or... Digital phase locked loop with selectable normal or...

2006-10-24

2006-10-24

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

C331S016000, C331S017000

Reexamination Certificate

active

07126429

ABSTRACT:
A digital phase locked loop with fast locking capability includes a digitally controlled oscillator for producing an output signal phase locked to an input reference clock, a phase detector for measuring the phase difference between said input reference clock and a feedback clock, and a loop filter for producing a control signal for the digitally controlled oscillator The loop filter includes a proportional circuit for developing a first signal proportional to said phase difference, an integrator for developing a second integrated signal from said first signal, an adder for adding said first and second signals to develop said control signal, and a weighting circuit, preferably a linear multiplier, for selectively adding extra weight to the first signal at an input to the integrator to shorten the locking time of the phase locked loop in a fast locking mode and to rapidly achieve a stable frequency in holdover mode.

REFERENCES:
patent: 5065115 (1991-11-01), Pletz-Kirsch et al.
patent: 5511100 (1996-04-01), Lundberg et al.
patent: 5612980 (1997-03-01), Ledda et al.
patent: 6614316 (2003-09-01), Masenas et al.
patent: 1104111 (2001-05-01), None
patent: 2331192 (1999-05-01), None
patent: 2357382 (2001-06-01), None

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