Digital phase locked loop with dithering

Details Digital phase locked loop with dithering Digital phase locked loop with dithering

2011-04-05

2011-04-05

Mai, Lam T (Department: 2819)

Coded data generation or conversion

Converter compensation

C375S376000, C331S017000

Reexamination Certificate

active

07920081

ABSTRACT:
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

REFERENCES:
patent: 7046098 (2006-05-01), Staszewski
patent: 7483508 (2009-01-01), Staszewski et al.
patent: 7570182 (2009-08-01), Sheba et al.
patent: 7777576 (2010-08-01), Waheed et al.
patent: 7786913 (2010-08-01), Waheed et al.

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