Digital phase locked loop with bounded jitter

Details Digital phase locked loop with bounded jitter Digital phase locked loop with bounded jitter

1987-11-18

1989-08-08

Heyman, John S.

Oscillators

Relaxation oscillators

331 1A, 331 11, 331 25, 328133, 377118, 307511, 307529, H03L 700, H03K 500

Patent

active

048556831

ABSTRACT:
A digital phase locked loop operable over a wide dynamic range has jitter performance that is exactly bounded within predetermined limits. The phase locked loop includes an accumulator-type digital voltage controlled oscillator (201) which generates from a high speed system clock, an output clock signal at frequency equal to p times the frequency of an input clock signal, and which output frequency is controlled by the value k of a digital input to the VCO. A frequency window comparator (208) compares the number of output clock pulses between input clock pulses to determine, based on the count, whether the frequency of the output is too high, too low or equal to the correct frequency. A phase window comparator (210) simultaneously determines from the phase of the output clock signal whether the phase is leading, lagging or within a prescribed window of acceptability. In response to these determinations, k-controller (217) increases k to increase the frequency of the VCO when the frequency window comparator indicates the frequency is low or the phase window comparator indicates the phase is lagging; alternatively, k is decreased when the frequency is high or the phase is leading. Adjustment continues until the output clock is at the proper frequency and phase of the output clock falls within the window of acceptability.

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Rae et al-"Variable Frequency Oscillator Using a Frequency Discriminator"-IBM Technical Disclosure Bulletin-vol. 27-No. 1A-Jun. 1984-pp. 355-357.

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