Digital phase locked loop with a digital voltage controlled osci

Details Digital phase locked loop with a digital voltage controlled osci Digital phase locked loop with a digital voltage controlled osci

1995-12-12

1997-09-02

Epps, Georgia Y.

Dynamic information storage or retrieval

Specific detail of information handling portion of system

Radiation beam modification of or by storage medium

369 59, 369 54, 369 48, 360 46, 360 51, 375376, H03L 708, G11B 700

Patent

active

056639457

ABSTRACT:
A digital PLL circuit in a recording information reproducing apparatus, wherein a sampled value is obtained by A/D converting a read signal read from a recording medium at a sampling timing according to a reproduction clock signal, a phase error occurring in the read signal is detected on the basis of the sampled value, an oscillation data signal sequence whose data value increases or decreases at a changing period corresponding to the phase error is generated, the oscillation data signal sequence is converted to an analog signal, an oscillation signal is formed, and a signal obtained by converting the oscillation signal to a square wave is set to a reproduction clock signal for sampling.

REFERENCES:
patent: 4975930 (1990-12-01), Shaw
patent: 5424882 (1995-06-01), Kazawa
patent: 5469415 (1995-11-01), Fujita et al.
patent: 5475715 (1995-12-01), Hase et al.
patent: 5521767 (1996-05-01), Weng et al.
patent: 5553104 (1996-09-01), Takashi et al.

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