Digital phase locked loop utilizing a multi-bit phase error inpu

Details Digital phase locked loop utilizing a multi-bit phase error inpu Digital phase locked loop utilizing a multi-bit phase error inpu

1990-05-02

1991-10-08

Harkcom, Gary V.

Boots, shoes, and leggings

375120, 375 22, G06F 1531, H03K 708, H03D 324

Patent

active

050560549

ABSTRACT:
A digital loop filter translates a multi-bit phase error input into a high resolution control signal utilizable as an advance-retard control for a multi-phase clock generator. The digital filter couples the multi-bit phase error input to the clock generator via a pulse density modulation (PDM) accumulator, providing multi-phase adjustment in a single sample clock cycle based on the overflow or underflow of the PDM accumulator. Variable PDM cycles are used to control loop filter bandwidth, permitting adjustable capture sequences. Thus, real proportional control of the multi-phase clock generator is limited only by the word size of the phase error input.

REFERENCES:
patent: 4689802 (1987-08-01), McCambridge
patent: 4700360 (1987-10-01), Visser

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