Digital phase-locked loop using a tapped delay line in a phase m

Details Digital phase-locked loop using a tapped delay line in a phase m Digital phase-locked loop using a tapped delay line in a phase m

1990-06-08

1991-05-21

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 14, 331 17, 331 25, H03L 7085

Patent

active

050178890

ABSTRACT:
A digital Phase-Locked Loop (PLL), comprising a voltage-controlled oscillator (VCO) and a phase meter including a delay line with taps, wherein phase measurements are effected by sending a pulse through the delay line and determining the location of this pulse in the delay line at the rate of the output signal of the VCO. This location is determined by a processing circuit connected to the taps, which circuit generates in response to the location found a VCO control signal corresponding therewith.

REFERENCES:
patent: 4224575 (1980-09-01), Mosley et al.
patent: 4543600 (1985-09-01), Bolger

Affiliated with

Also associated with

Rating

Digital phase-locked loop using a tapped delay line in a phase m does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital phase-locked loop using a tapped delay line in a phase m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital phase-locked loop using a tapped delay line in a phase m will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-241111