Digital phase locked loop synchronizer

Details Digital phase locked loop synchronizer Digital phase locked loop synchronizer

1985-12-05

1987-06-30

Griffin, Robert L.

Pulse or digital communications

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375 82, 328 56, H03D 324

Patent

active

046776486

ABSTRACT:
A phase locked loop (PLL) arrangement comprising a local crystal oscillator (23) and a tapped delay chain (15) of analog delay elements (17). Connected to the delay chain taps are a flash register (25) consisting of latches which store the tap signal values at each data signal transition, and an output multiplexer (37) for selecting one of the tap signals as phase shifted output clock. Contents of the flash register are encoded by an encoder (33) which furnishes a value representing the phase offset between data signal and local clock signal. By a look-up table (41), the phase offset is converted to a phase selection value controlling the output multiplexer. The delay chain serves two purposes: Phase offset detection and clock signal phase shifting. No sampling or control signals are used which have a higher frequency than that of the system clock.

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Homan, "Electronically Adjustable Computer Clock System", IBM Technical Disclosure Bulletin, vol. 15, No. 1, Jun. 1972.

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