Digital phase-locked loop (PLL) having multilevel phase comparat

Details Digital phase-locked loop (PLL) having multilevel phase comparat Digital phase-locked loop (PLL) having multilevel phase comparat

1996-04-25

1997-12-02

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327144, 327147, 327160, 331 1A, 331 25, H03L 706

Patent

active

056940688

ABSTRACT:
Using positive-phase or negative-phase clocks of phase count clock Pf.sub.0, a number M of multilevel quantized phase comparators output as values quantized in multiple levels the phase differences of output signals outputted from first and second N-stage frequency dividers wherein input clocks and output clocks, respectively, of a digital PLL have been N-stage frequency divided and moreover, divided into M groups. An adder adds this phase difference information and outputs advanced pulses or delayed pulses. An N1 counter counts up in response to advanced pulses and both outputs an increment pulse and undergoes setting to initial value N1 upon counting up to 2N1. In response to delayed pulses, the N1 counter counts down, and upon counting down to "0" both outputs a decrement pulse and undergoes setting to initial value N1.

REFERENCES:
patent: 4808884 (1989-02-01), Hull et al.
patent: 5268653 (1993-12-01), Lafon
patent: 5463351 (1995-10-01), Marko et al.
patent: 5552727 (1996-09-01), Nakao
Yoshinori Rokugo et al., "Digital Phase Locked Loop Used for the Stuffing Synchronization Systems", Electronic Information Communications Conference Papers, BI, vol. J73-B-I, No. 8, Aug. 1990, pp. 650-659.

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