Digital phase-locked loop for speed measurement, in particular f

Details Digital phase-locked loop for speed measurement, in particular f Digital phase-locked loop for speed measurement, in particular f

1976-05-03

1977-09-13

Blix, Trygve M.

Fluid-pressure and analogous brake systems

Pipeless valves

303 20, 307233B, 324161, 361238, B60T 808

Patent

active

040477665

ABSTRACT:
A digital phase-locked loop for speed measurement, in particular for use in antiskid control systems, for the conversion of the frequency of an input pulse sequence, proportional to a speed, into a digital numerical value to be used in the digital arithmetic unit for an antiskid control system is provided wherein there is a certain numerical value which will always be the same which is allocated to any input pulse sequence and which can be applied to a first storage register and added to the contents therein. At regular intervals, determined by a clock generator, a positive digital output numerical value is generated by a detector if the content of the first storage register is above a predetermined upper limit and a negative digital output numerical value will be generated if the contents of the first storage register are below a predetermined lower limit. Furthermore, the respective digital output numerical value of the detector can be added to the content of a second storage register, observing a correct sign. The contents of the second storage register are at digital numerical value corresponding to the frequency of the input pulse sequence, with that digital numerical value always being subtracted from the content of the first storage register upon each clock pulse generated by the clock generator.

REFERENCES:
patent: 3746925 (1973-07-01), Schaepman
patent: 3838889 (1974-10-01), Miller
patent: 3843210 (1974-10-01), Portas

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