Digital phase locked loop circuitry and methods

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S153000

Reexamination Certificate

active

07138837

ABSTRACT:
Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal.

REFERENCES:
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patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2002/0190751 (2002-12-01), Lee et al.
patent: 2003/0006808 (2003-01-01), Weng et al.
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patent: 2003/0052709 (2003-03-01), Venkata et al.
patent: 2004/0085974 (2004-05-01), Mies et al.
patent: 1 113 616 (2001-07-01), None
U.S. Appl. No. 10/059,014, filed Jan. 29, 2002, Lee et al.
U.S. Appl. No. 10/273,899, filed Oct. 16, 2002, Venkata et al.
U.S. Appl. No. 10/317,262, filed Dec. 10, 2002, Venkata et al.
U.S. Appl. No. 10/317,264, filed Dec. 10, 2002, Venkata et al.

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