Digital phase-locked loop circuit with reduced phase jitter...

Details Digital phase-locked loop circuit with reduced phase jitter... Digital phase-locked loop circuit with reduced phase jitter...

2000-11-13

2001-09-04

Wong, Peter S. (Department: 2815)

Electricity: power supply or regulation systems

Output level responsive

Phase controlled switching using electronic tube or a three...

C323S241000, C323S322000

Reexamination Certificate

active

06285172

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of integrated circuits, and is more specifically directed to circuitry for synchronizing clocked integrated circuits with an external clock.
As is fundamental in the art, many modern electronic systems now include numerous integrated circuits that operate in conjunction with one another. Particularly in complex high performance systems such as modern personal computers and workstations, these integrated circuits typically operate in a synchronous manler relative to a system clock. Examples of these integrated circuits include the central processing unit (CPU) of the system, typically an instruction-programmable device such as a microprocessor or digital signal processor (DSP), other programmable devices such as memory controllers, timers, and input/output devices, and also general purpose digital logic for controlling system operation and communication. In smaller systems, such integrated circuits may also correspond to custom control functions. Many modern digital logic integrated circuits are now realized in a semi-custom manner, for example by way of a gate array, or by way of an application specific integrated circuit (ASIC) which implements a selected arrangement of circuit functions into a single integrated circuit.
Because of the finite resistance of conductive lines and differences in signal distance among the integrated circuits, as well as variations in propagation delay among the various circuits in a system, the synchronous operation of the integrated circuits in a system is not inherently guaranteed. Differences in the instantaneous phase of clock signals within an integrated circuit and among multiple integrated circuits in the system, and also variations in these phase differences over time, require delay stages or wait states in the operation of the integrated circuits to ensure reliable synchronous operation and signal communication within a system or subsystem. In order for the overall performance of the system to be maximized, it is important that the synchronous operation of each circuit be synchronized with the system clock itself, and thus with one another.
A conventional approach for synchronizing the operation of an integrated with a system clock is the well-known phase-locked loop, or PLL. PLLs are often deployed in clock distribution circuitry of an integrated circuit, so that internal clock signals may be generated and distributed within the circuit that are maintained at a fixed phase relationship relative to the system clock. Each integrated circuit in the system that utilizes a PLL to generate such phase-synchronous internal clocks will therefore be operating synchronously (i.e., in a fixed phase relationship) with one another, minimizing the necessity of delay in the communication of signals among these synchronized circuits.
In general, PLL circuits operate by comparing the time at which an edge of the system clock is received relative to a corresponding edge of an internally generated clock. If a significant delay between these two edges is detected, the generation of the internal clock is adjusted to more closely match the received system clock. To accomplish this, PLL circuits in modern circuits may be realized in either analog or digital form. In an analog PLL, the frequency of a periodic signal produced by a voltage controlled oscillator is adjusted in response to a filtered signal from a phase detector, such that the instantaneous frequency of the internal chip clock is advanced or retarded depending upon whether the chip clock lags or leads the system clock. Analog PLLs therefore adjust the phase of the chip clock in a substantially continuous manner in response to a phase difference between the internal chip clock and the system clock; this smooth operation generally depends upon the filtering of the output of the phase detector circuit, but can be made quite well-behaved in most implementations. However, analog PLL are typically somewhat complex to implement, especially in high performance digital integrated circuits.
In a digital PLL, the length of a digital delay line is adjusted in response to the chip clock leading or lagging the system clock.
FIG. 1
illustrates a generalized block diagram of a conventional digital PLL. As shown therein, the system clock is applied to a first input of phase detector
11
, and to an input (A) of digital delay line
15
; a chip clock signal generated by the PLL itself is applied to a second input of phase detector
11
. In this conventional digital PLL, digital delay line
15
is a controllable series of delay stages by way of which its output signal (Y) is generated as a delayed version of the incoming system clock signal, with an adjustable delay therebetween. A shift clock on line CLK is also generated by phase detector
11
, in response to a phase difference between the chip and system clocks, and is applied to digital delay line
15
to shift a tap point therein in a direction corresponding to the state of line R/{overscore (L)} from phase detector
11
. The control signal on line R/{overscore (L)} is generated by phase detector
11
according to the polarity of the phase difference between corresponding edges of the system clock signal and the chip clock signal. Clock distribution circuitry
17
receives the output clock signal (Y) from digital delay line
15
, and generates and distributes clock signals throughout the remainder of the corresponding integrated circuit, including the chip clock signal that is applied to phase detector
11
.
In operation, phase detector
11
generates a pulse of its shift clock on line CLK in response to detecting a phase difference between the system clock and the chip clock signal that exceeds a threshold time. This shift clock pulse from phase detector
11
shifts the position of a tap point within digital delay line
15
to adjust its delay length between the receipt of an edge at input A and the generation of the edge at output Y; the adjustment is made in the direction indicated by the state of line R/{overscore (L)} from phase detector
11
. In response to the chip clock signal leading the system clock, phase detector
11
will drive line R/{overscore (L)} high so that, upon a pulse of the shift clock on line CLK, digital delay line
15
lengthens its delay by one step, further delaying the output signal from the system clock signal. Conversely, if the system clock is leading the chip clock signal, phase detector
11
drives a low level on line R/{overscore (L)}, to reduce the delay in digital delay line
15
upon receipt of a shift clock pulse on line CLK, incrementally advancing the chip clock signal relative to the system clock. Over a sufficient number of cycles and adjustments, the conventional digital PLL of
FIG. 1
will eventually generate and distribute clock signals that are in a fixed phase relationship with the system clock.
As compared with analog PLLs, digital PLLs are relatively straightforward to implement and simulate in the design cycle, and generally exhibit good noise immunity. Additionally, considering that no external components are typically required for digital PLLs and that the digital PLL may be realized by similar circuit elements as used elsewhere in the digital integrated circuits, many modern integrated circuits now include digital PLL circuitry for synchronizing their internally generated on-chip clocks with external system clocks.
As noted above, analog PLLs adjust the chip clock phase in a substantially continuous manner. In contrast, however, digital PLLs can only adjust the phase relationship between the internal chip clock and the system clock to a discrete accuracy that corresponds to the minimum step size of the digital delay line. This granularity is due to the operation of the digital PLL, once the chip clock reaches substantially the phase of the system clock, in adding or subtracting the smallest delay step to or from the

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