Digital phase locked loop circuit

Details Digital phase locked loop circuit Digital phase locked loop circuit

1989-06-12

1990-12-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307511, H03K 522, H03L 700

Patent

active

049756516

ABSTRACT:
A phase locked loop circuit for producing a control signal with a predetermined phase relationship to an input signal includes a first counter which counts a reference clock signal and is supplied from a control circuit with first and second signals. The first counter operates in a normal mode in which a count value is changed one by one when both, the first and second signals are not supplied, in a skip mode in which a first predetermined count value is skipped when the first signal is supplied, and in a repeat mode in which a second predetermined count value is repeated when the second signal is supplied. A second counter is provided, which perform a count operation in synchronism with the reference clock signal under the control of an output of the first counter to produce the control signal. The loop circuit further includes a phase comparator which produces phase difference data representative of a phase difference between the input signal and the control signal. The control circuit supplies the first and second signals to the first counter in response to the phase difference data to command the first counter so as to operate in one of the normal, skip and repeat modes a plurality of times during one cycle period of the control signal.

REFERENCES:
patent: 3621403 (1969-03-01), Seiy
patent: 3629503 (1969-04-01), Rempert
patent: 3952253 (1976-04-01), Devolpi
patent: 4089060 (1978-05-01), Mitchell
patent: 4573176 (1986-02-01), Yeager
patent: 4606058 (1986-08-01), Kruger
patent: 4780895 (1988-10-01), Paul

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