Digital phase locked loop circuit

Details Digital phase locked loop circuit Digital phase locked loop circuit

1988-05-11

1989-04-11

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

331 14, 328155, 360 43, H03K 5135

Patent

active

048212938

ABSTRACT:
A digital phase locked loop (PLL) circuit having an input terminal to which an input digital signal is supplied, a counter for counting a reference clock, a digital phase comparator for comparing the phases of the input digital signal and the output of the counter, a digital low-pass filter supplied with the output of the digital phase comparator, a correction control signal generating circuit and a control circuit, whereby the quantization error is reduced to improve the follow-up characteristic of the digital PLL circuit. Also, the digital PLL circuit contains no residual phase error and this highly-stable digital PLL circuit is arranged so as not to respond to a high frequency fluctuation component such as a peak shift.

REFERENCES:
patent: 4493094 (1985-01-01), Thomson

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