Digital phase locked loop circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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327105, 327261, 327277, 327156, 327158, 327147, 327149, 331DIG2, 331 17, H03K 5159, H03L 7189

Patent

active

055527272

ABSTRACT:
A digital circuit apparatus having an A/D converter for digitalizing a control voltage which determines the oscillation frequency of an internal clock outputted from a voltage-controlled oscillator, a storing unit for holding a digitalized value, a D/A converter with corrective function for correcting the digital value being held and subjecting the corrected digital value to D/A conversion, and a lock detector for detecting the matching in phase of the internal clock and an external clock. Phase information obtained when the internal clock and the external clock match in phase is held so that, when the generation of the internal clock outputted from the voltage-controlled oscillator is halted and then resumed, the matching in phase of the external clock and internal clock can be achieved in a short period of time.

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"Phase lock loop with delay line oscillator", Laurich et al., IBM Technical Disclosure Bulletin, vol. 13, No. 7 Dec. 1970, pp. 1863-1864.
"Design of PLL-Based Clock Generation Circuits", Deog-Kyoon Jeong et al., IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987.
"A Variable Delay Line PLL for CPU-Coprocessor Synchronization", Mark Johnson et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.

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