Digital phase-locked loop and digital phase-frequency...

Details Digital phase-locked loop and digital phase-frequency... Digital phase-locked loop and digital phase-frequency...

2009-08-30

2011-11-15

O'Neill, Patrick (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S003000, C327S007000, C327S012000, C327S147000, C327S150000, C327S159000, C331S00100A, C331S025000, C331S00100A, C375S375000, C375S376000

Reexamination Certificate

active

08058915

ABSTRACT:
A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.

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Article Titled “A Low-Noise Wide-BW 3.6-GHz Digital Σ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation” authored by Chun-Ming Hsu et al., in IEEE JSSCCC, vol. 43, No. 12, 2008, pp. 2776-2786.

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