Digital phase-locked loop

Details Digital phase-locked loop Digital phase-locked loop

1990-05-15

1992-09-15

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

329303, 375 82, 375108, H03D 322

Patent

active

051484501

ABSTRACT:
An external digital phase locked loop for use in connection with a conventional serial communication controller is driven by a clock whose frequency is ten times the nominal data rate. Bit cells are divided into ten contiguous states. An adjustment window encompasses two states on either side of the nominal bit cell boundary. If a data transition is detected in either of two states later than the cell boundary, the bit cell timing is extended by one full state. On the other hand, if a data transition is detected in either of two states earlier than the nominal bit cell boundary, the bit cell timing is decreased by one full state.

REFERENCES:
patent: 3925614 (1975-12-01), Bousmar
patent: 4330863 (1982-05-01), Wright
patent: 4561098 (1985-12-01), Tol
patent: 4584695 (1986-04-01), Wong et al.
patent: 4821293 (1989-04-01), Shimizume et al.

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