Digital phase locked loop

Details Digital phase locked loop Digital phase locked loop

2007-09-18

2007-09-18

Ghayour, Mohammed (Department: 2611)

Pulse or digital communications

Testing

Phase error or phase jitter

C375S377000, C375S376000, C375S355000

Reexamination Certificate

active

10137986

ABSTRACT:
Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

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