Digital phase locked loop

Details Digital phase locked loop Digital phase locked loop

2005-08-16

2005-08-16

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Receivers

Angle modulation

C329S308000

Reexamination Certificate

active

06931082

ABSTRACT:
A technique that enables the sine and cosine branches within a PLL module to be obtained relatively easily and efficiently is described. According to the technique, the computation operations requiring a computation load, such as calculation of sine and cosine functions, are performed mostly once per a digital sampled signal, while relatively simple operations, such as multiplication and accumulations, are performed for every frame.

REFERENCES:
patent: 4285044 (1981-08-01), Thomas et al.
patent: 4761751 (1988-08-01), Canniff
patent: 4888719 (1989-12-01), Yassa
patent: 4905177 (1990-02-01), Weaver, Jr. et al.
patent: 5113361 (1992-05-01), Damerow et al.
patent: 5159435 (1992-10-01), Holmbo et al.
patent: 5631586 (1997-05-01), Sogo
patent: 6154483 (2000-11-01), Davidovici et al.
patent: 6735263 (2004-05-01), Moriya et al.
Jacob Klapper and John T. Frankle,Phase-Locked and Frequency Feedback Systems, Academic Press, New York, 1972; Ch. 8.

Affiliated with

Also associated with

Rating

Digital phase locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital phase locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital phase locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3487540