Digital phase locked loop

Details Digital phase locked loop Digital phase locked loop

1999-05-17

2001-02-06

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S150000, C327S147000

Reexamination Certificate

active

06184734

ABSTRACT:

The present invention relates to a Phase Locked Loop (PLL) implemented in a digital form.
As is well knowm a PLL's function is to provide an oscillating output which is synchronised or locked with an incoming signal. The generation of the output signal is independent of the incoming signal although its phase is controlled by the incoming signal. Therefore a PLL is useful for, for example, generating a clock signal synchrornised with an incoming signal. while the incoming signal may be affected by noise or may be partially corrupted. A typical analog PLL comprises three basic elements: a phase comparator for receiving an incoming signal with which it is desired to lock a loop filter to process a current error signal and an integrator to adjust the output to account for the error.
In particular in communication systems it is necessary to recover a correct clock signal from the received data in order that the received data can be properly understood. In digital communication systems an analogue PLL could be provided for the generation of the clock signal. but implementation of an entirely digital svstem would be simplified by the provision of a digital PLL (DPLL) such that it can be integrated with other parts of the digital device.
The present invention provides a DPLL in which the above elements are implemented digitally such that it can be implemented using standard logic synthesis tools. This means that the invention is not limited to a particular type of chip, for example, but can be easily imnplemented in many digital environments and different format integrated circuits.
The DPLL of the present invention, while advantageously used for recovery of clock signals in a digital data communications system as mentioned above. can also be utilised in other situations where a PLL function is required in a digital environment.
The present invention implements a method of generating an output signal synchronised with an input signal comprising providing a plurality of candidate signals and selecting one of said candidate signals as the output signal according to a phase comparison between the candidate signals and the input signal.
The phase comparison is preferably conducted by sampling the candidate signals according to the input signal and utilizing the results of the sampling to generate an error signal indicative of the phase difference between the currently selected output signal and the input signal. The error signal is then fed back to select a new candidate signal as the output signal.
To avoid “hunting” in the selection feed-back the method preferably further comprises attenuating the error signals progressively to achieve a satisfactory “lock” with the input signal while being unaffected by noise and jitter in the input signal .


REFERENCES:
patent: 4999528 (1991-03-01), Dudley
patent: 5034967 (1991-07-01), Cox et al.
patent: 5040193 (1991-08-01), Leonowich

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