Digital phase-locked loop

Pulse or digital communications – Spread spectrum – Direct sequence

Patent

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Details

375 94, 331 1A, 329122, H04L 708

Patent

active

043609260

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to a digital phase-locked loop, preferably for bit rate regeneration in synchronous data transmission systems, which transfer from a transmitter to a receiver redundantly coded information, modulated in a suitable mode.


DESCRIPTION OF PRIOR ART

In order that a data signal can be regenerated correctly at the receiver side in a synchronous data transmission system, the information about, inter alia, bit rate and bit phase must be available in the receiver. It is previously known to utilize a phase-locked loop controlled by, for example, zero level crossings, in the transmitted base band signal for regeneration of the bit rate.


BACKGROUND OF THE INVENTION

In data transmission systems of the kind mentioned above, there is sometimes the risk that the bit rate regenerator locks in an incorrect phase position even if the frequency is correct per se. This means that the data detector of the system does not sample in the centre of the eye of the eye pattern of the transmitted signal, and the resulting bit error frequency will thus be high. As the phase-locked loop only sporadically receives relevant control information to get itself out of this state, correct synchronization can require a relatively long time. This is naturally a clear disadvantage for all systems of this kind and is especially troublesome in a system for two-way communication on the same channel, for example, i.e. alternating transmission and reception from each terminal. For such systems the synchronization sequence will of course be especially frequent.


SUMMARY OF THE INVENTION

The phase-locked loop in accordance with the present invention, the distinguishing features of which are apparent from the accompanying claims, solves the above technical problem, providing that the transmitted signal is redundantly coded in some respect. Above all, the solution gives the advantage that the synchronization time, e.g. when starting up, is greatly reduced by preventing locking in an incorrect phase-position.


BRIEF DESCRIPTION OF THE DRAWING

The invention will now be described while referring to the accompanying drawing, whose sole FIGURE illustrates an embodiment of the phase-locked loop in accordance with the invention.


PREFERRED EMBODIMENTS

In the following description, it is assumed that the receiver can discover errors in the transmitted data flow. There is this possibility, e.g. when data is transferred with a parity bit or with redundant data coding. Such coding signifies that the transmitted signal elements are correlated, e.g. as with base band coding according to the Partial-Response concept, bi-phase coding, AMI-coding (Alternate Mark Inversion), Miller coding etc.
The correlation between the signal elements in these codes is primarily introduced to obtain a suitable spectral distribution for the transmission, but can thus also be used for enabling error detection on the receiver side.
If AMI-coding is taken as an example, then the binary information "1" is transmitted with pulses which alternate in polarity, and the binary information "0" with an excluded pulse, i.e. zero level. With a simple check that the pulses alternate in polarity in the received base band signal in the detector, detection errors, or bipolar violations (BPV) can be discovered.
When the regenerated bit rate is synchronized to the right phase position for controlling the time when the data detector senses and detects the base band signal, BPV only occurs because of disturbances in the data transmission itself. On the other hand, if the regenerated bit rate is out of phase e.g. during the synchronization sequence, or during incorrect locking of its phase position, the number of BPV's increases very greatly.
The FIGURE illustrates a part of the receiver in a transmission system in accordance with the above. The transmitted data signal, demodulated where applicable, arrives at the data detector 2 of the receiver, where it is sampled. In a following operation it is decoded in the decoder 7. A bit rate extraction

REFERENCES:
patent: 4030045 (1977-06-01), Clark
patent: 4085288 (1978-04-01), Viswanathan
patent: 4151485 (1979-04-01), La Fratta

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