Digital phase locked circuit with shortened lock time

Details Digital phase locked circuit with shortened lock time Digital phase locked circuit with shortened lock time

1997-06-24

1999-08-31

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327158, 327160, H03K 513

Patent

active

059458569

ABSTRACT:
A clock control circuit 10 generates a reference clock signal CK.sub.2 in accordance with a clock signal CLK, performs a phase comparison with an oscillation signal S50 from a programmable mask generation circuit 50 at a phase comparator 20, generates an up signal S.sub.up or a down signal S.sub.dw in accordance with the result of comparison, and outputs the same to a counter 30. The counter 30 sequentially determines values of the bits from the most significant bit to the least significant bit, outputs the count S30 to a digital control delay line 40, and controls the frequency of an oscillation signal S40. After reaching the locked state, the counter 30 sequentially determines the values of bits from the least significant bit to the most significant bit in accordance with the up/down signal and tracks the reference clock signal CK.sub.2, therefore the lock up time of the digital PLL circuit can be shortened.

REFERENCES:
patent: 5087829 (1992-02-01), Ishibashi
patent: 5173617 (1992-12-01), Alsup
patent: 5493243 (1996-02-01), Ghoshal
patent: 5506868 (1996-04-01), Chiang
patent: 5548235 (1996-08-01), Marbot
patent: 5757868 (1998-05-01), Kelton

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