Digital phase-lock loop system with analog voltage controlled os

Details Digital phase-lock loop system with analog voltage controlled os Digital phase-lock loop system with analog voltage controlled os

1990-10-18

1992-06-23

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307269, 307219, 307602, 328 63, 328 72, 328155, 331 2, 331 11, 331 47, 331 55, H03K 500, H03K 513

Patent

active

051245698

ABSTRACT:
A phase-lock loop scheme which can be implemented in an application specific integrated circuit using CMOS elements is disclosed which is directed to controlling a plurality of slave gate array circuits such that each of the master gate array circuit and the slave gate array circuits are clocked at the same time and are within a fixed time delay from a device reference clock signal. The master gate array circuit receives the input clock synchronization signal from the master clock of the device containing the master and gate array circuits and produces an internal clock signal which is then sent to each of the slave gate array circuits, by means of equal delay paths. The phase-lock loop circuitry utilized by each of the gate arrays can be implemented on program logic array chips along with the logic which receives the synchronized clock signals generated by the respective phase-lock loops of each of the gate array chips. Both fixed and automatic gain and damping controls for the phase-lock loops are also disclosed.

REFERENCES:
patent: 3600699 (1971-08-01), Orenberg
patent: 3806879 (1989-02-01), Troxel
patent: 4239982 (1980-12-01), Smith et al.
patent: 4282493 (1981-08-01), Moreau
patent: 4500851 (1985-02-01), Sawa et al.
patent: 4651103 (1987-03-01), Grimes
patent: 4691126 (1987-09-01), Splett et al.
patent: 4779008 (1988-10-01), Kessels
patent: 4868522 (1989-09-01), Popat et al.

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