Digital phase-lock loop having an estimator and predictor of err

Details Digital phase-lock loop having an estimator and predictor of err Digital phase-lock loop having an estimator and predictor of err

1987-08-13

1988-09-13

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 25, 328155, H03L 708

Patent

active

047712503

ABSTRACT:
A digital phase-lock loop (DPLL) which generates a signal with a phase that approximates the phase of a received signal with a linear estimator. The effect of a complication associated with non-zero transport delays related to DPLL mechanization is then compensated by a predictor. The estimator provides recursive estimates of phase, frequency, and higher order derivatives, while the predictor compensates for transport lag inherent in the loop.

REFERENCES:
patent: 4418318 (1983-11-01), Swagerty et al.
patent: 4577163 (1986-03-01), Culp
patent: 4712223 (1987-12-01), Nelson

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