Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation
Reexamination Certificate
2000-06-01
2003-10-28
Kincaid, Lester G. (Department: 2681)
Telecommunications
Receiver or analog modulated signal frequency converter
Local control of receiver operation
C455S557000, C370S474000, C375S355000, C375S375000
Reexamination Certificate
active
06640094
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wireless communication apparatus which is connected to a digital line.
2. Description of the Related Art
In recent years, with the widespread use of digital networks, such as ISDN (Integrated Services Digital Network), it has become possible for data terminals, such as personal computers, to be connected to the ISDN via terminal adapters, and data processed by a data terminal can be transmitted and received.
In such a case, a data terminal is connected to a terminal adapter through cables by RS232C, and data is transmitted from a personal computer to the terminal adapter by a start-stop synchronous method at transmission speeds, such as 2400 bps, 4800 bps, 9600 bps, 19.2 kbps, or 38.4 kbps. The terminal adapter receiving the data converts it into a transmission speed of 64 kbps in conformance with V.110, I.460 of the ITU (International Telecommunications Union) standard recommendations and transmits it to the ISDN.
Also, with the widespread use of digital wireless systems, such as a PHS (Personal Handy-phone System), terminals which perform wireless data transmission are put into practical use. In a case in which wireless data transmission is performed using a PHS, in order that retransmission control is performed among terminals, frames of a predetermined format are formed and data transmission is performed.
In Japan, as a PIAFS (PHS Internet Access Forum Standard), a wireless data transmission protocol is standardized. Use of this wireless data transmission protocol makes it possible to realize wireless data communication using data terminals.
Also, by combining the ISDN with the PHS, communication of voice data and various types of data by wire and by wireless via public lines are made possible.
A wireless communication system described in a U.S. patent application (U.S. patent application Ser. No. 100,208, Application date: Jun. 19, 1998) filed by the present inventors is shown in FIG.
27
.
As shown in
FIG. 27
, a PHS base unit
1002
, a data terminal
1003
, such as a personal computer, and a facsimile apparatus
1004
are connected to an ISDN
1000
via a terminal adapter
1001
, and a scanner
1006
and a printer
1007
are connected to the data terminal
1003
, so that speech from a PHS telephone set
1005
, image data read by a scanner, etc., can be transmitted via the ISDN
1000
.
As described above, when data communication is performed via the ISDN
1000
, an addition circuit for establishing synchronization with the network (the ISDN
1000
) is required, and a synchronization process therefor is performed by the terminal adapter (TA)
1001
.
FIG. 28
is a schematic block diagram showing an example of the construction of the TA
1001
for performing a network synchronization process studied by the present inventors.
As shown in
FIG. 28
, the TA
1001
comprises a CPU
1100
, a memory
1101
, a bus
1102
, an ISDN interface
1103
, an HDCL (High-level Data Link Control) controller
1104
, a PLL (Phase-Locked Loop) circuit
1105
, a low-pass filter
1106
, a TCVCXO (Temperature Compensated Voltage Controlled Crystal Oscillator)
1107
, a baseband processing section (BBIC)
1108
, an RS232C controller
1110
, etc.
In a case in which data (including PCM (Pulse Code Modulation)-coded speech) is transmitted and received between a PHS and the ISDN
1000
, it is required that the ISDN line
1000
and the PHS wireless line operate in synchronization with each other in order to prevent overrun and underrun of data.
For this reason, in the TA
1001
in
FIG. 28
, the construction is formed in such a way that synchronization with the network (ISDN
1000
) is established by using the PLL circuit
1105
, the low-pass filter
1106
, and the TCVCXO
1107
.
A clock used in the PHS which is a digital wireless communication apparatus connected to the ISDN
1000
requires a very high frequency stability of a frequency of ±3 ppm and a transmission speed accuracy of ±5 ppm in accordance with the standard specification of RCR ST (Research & Development Center for Wireless Systems Standards)-
28
.
In spite of the fact that the synchronization timing accuracy of the PHS wireless line requires a high accuracy of within ±5 ppm, the accuracy of the synchronization timing clock extracted from the ISDN
1000
is not accurate to the level of ±5 ppm.
Therefore, it can be conceived that the synchronization system comprising the TCVCXO
1107
and the PLL circuit
1105
, shown in
FIG. 28
, corrects a 64 kHz clock
1112
generated by the baseband processing section
1108
by the 64 kHz clock
1112
synchronized with the ISDN
1000
and a 19.2 MHz clock generated by the TCVCXO
1107
, so that the TCVCXO
1107
is controlled to operate by this corrected clock.
In the TCVCXO
1107
, the output frequency is within 19.2 MHz ±3 ppm regardless of the magnitude of the input voltage.
The baseband processing section
1108
generates a 64 kHz clock
1113
on the basis of the output clock of the TCVCXO
1107
. The two clocks, the 64 kHz clock
1113
and the 64-kHz clock (ISDN clock)
1112
synchronized with the ISDN, are input to the PLL circuit
1105
.
The PLL circuit
1105
compares the phase of the 64 kHz clock
1113
generated in the baseband processing section
1108
with the phase of the ISDN clock
1112
. When the phase of the ISDN clock
1112
leads, a pulse of 5 V is output, and when the phase of the ISDN clock
1112
lags, a pulse of 0 V is output.
The output pulse of the PLL circuit
1105
is smoothed by the low-pass filter
1106
, and this smoothed signal is input, as a voltage control signal, to the TCVCXO
1107
, allowing the oscillation frequency of the TCVCXO
1107
to be controlled.
More specifically, if the phase of the ISDN clock leads, the control voltage of the TCVCXO
1107
is increased, the output frequency of the TCVCXO
1107
becomes higher, heading toward a direction in which the output of the TCVCXO
1107
and the phase of the ISDN clock
1112
match. Conversely, if the phase of the ISDN clock lags, the control voltage of the TCVCXO
1107
is decreased, and the output frequency of the TCVCXO
1107
becomes lower, heading toward a direction in which the output of the TCVCXO
1107
and the phase of the ISDN clock
1112
match.
The output of the TCVCXO
1107
, the synchronization of which with the ISDN clock
1112
is established in this manner, is input to the baseband processing section
1108
, and the baseband processing section
1108
generates a 64 kHz clock
1113
on the basis of the output signal of the TCVCXO
1107
, with the result that the synchronization between the 64 kHz clock
1113
generated in the baseband processing section
1108
and the ISDN clock
1112
is established.
As described in Japanese Patent Laid-Open No. 7-307969, a digital wireless communication apparatus has been conceived which comprises a first clock source synchronized with the digital network, a second clock source for supplying a clock with an accuracy higher than that of the first clock source, a first speech path unit which operates in synchronization with the first clock source or the second clock source, and a second speech path unit which operates in synchronization with the second clock source, wherein a speech path unit is selected according to whether it is an extension communication or an outside line communication.
In RCR ST-
28
, it is specified that the absolute accuracy of the frequency stability is ±3 ppm, and the absolute accuracy of the transmission speed indicating the accuracy of burst transmission and reception at intervals of 5 milliseconds between a base station and a mobile station is ±5 ppm.
In the manner as described above, in spite of the specification that the absolute accuracy of the transmission speed is less stringent than the absolute accuracy of the frequency stability, in the TA
1001
in
FIG. 28
, a clock related to transmission is generated based on a reference frequency having a high accuracy, in which the frequency stability i
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Kincaid Lester G.
Ward Ronald J.
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