Digital phase lock loop decoder

Details Digital phase lock loop decoder Digital phase lock loop decoder

1990-03-14

1991-03-26

Olms, Douglas W.

Pulse or digital communications

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370108, 328 55, H03D 324

Patent

active

050035622

ABSTRACT:
A digital phase lock loop decoder for use in decoding Manchester encoded data operates at an internal clock speed having a speed equal to the data rate of the encoded data. The decoder includes a first sampling circuit for providing signals based on the clock speed of the encoded data, a delay circuit for generating delayed clock signals relative to the clock speed of the encoded data, a second sampling circuit for sampling the encoded data based on the delayed clock signals, a feedback circuit for generating clock signals whose phase corresponds with the phase of the delayed clock signals and a storage for outputting decoded data signals corresponding to the encoded data utilizing the delayed clock signals.

REFERENCES:
patent: 4584695 (1986-04-01), Wong et al.
patent: 4627080 (1986-12-01), Debus, Jr.
patent: 4661965 (1987-04-01), Maru
patent: 4709170 (1987-11-01), Li
patent: 4780889 (1988-10-01), Ley et al.
patent: 4795985 (1989-01-01), Gailbreath, Jr.
patent: 4841167 (1989-06-01), Saegusa
patent: 4841551 (1989-06-01), Avaneas

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