Digital phase lock loop circuit and method

Oscillators – Relaxation oscillators

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Details

328 63, 331 25, 331 1A, H03K 117

Patent

active

041433289

ABSTRACT:
A digital phase lock loop circuit and method wherein the phase and the frequency of an output clock pulse of the circuit are made to instantaneously coincide with the phase and the frequency of an input clock pulse of the circuit. The digital phase lock loop circuit includes a fixed frequency generator circuit, an output frequency divider to which a standard clock pulse from the fixed frequency generator circuit is supplied via an inhibit gate, an output clock pulse frequency divider which divides the frequency of the output clock pulse from the output frequency divider, a phase comparator to which the input clock pulse and the divided clock pulse from the output clock pulse frequency divider are provided and an inhibit pulse generator to which the output of the phase comparator is supplied, so as to provide an inhibit pulse from the inhibit pulse generator to the inhibit gate. Further, according to the present invention, a clear pulse generator is provided for the purpose of forming a clear pulse which clears the contents of the output frequency divider and the output clock frequency divider. Such clear pulse is generated based on the condition that the time difference between a first occurrence (the frequency division of the output frequency divider being actuated by the standard clock pulse after the output frequency divider, and the output clock frequency divider being cleared by the clear pulse) and a second occurrence (the frequency division of the input frequency divider being actuated by the input clock pulse) is smaller than a predetermined period of the standard clock pulse.

REFERENCES:
patent: 3781695 (1973-12-01), Jackson
patent: 3870970 (1975-03-01), Chibana
patent: 3872397 (1975-03-01), Hanneman
patent: 3988696 (1976-10-01), Sharpe
patent: 4001713 (1977-01-01), Egan

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