Digital phase lock loop

Details Digital phase lock loop Digital phase lock loop

2006-10-03

2006-10-03

Callahan, Timothy P. (Department: 2816)

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

C327S159000

Reexamination Certificate

active

07116743

ABSTRACT:
Techniques of designing a digital phase lock loop are disclosed. In one embodiment, the digital phase lock loop comprises a synchronization unit producing a producing a plurality of clock signals in accordance with a seed clock signal having a frequency, each of the clock signals having a modified frequency over the frequency of the seed clock signal and a phase shift from each other; a phase-frequency detection unit receiving an input signal and a feedback signal, and sampling the input signal and the feedback signal in accordance with the clock signals to determine differences in phase and frequency between the input signal and the feedback signal; a digital control oscillator receiving the clock signals and producing an output signal in reference to the differences from phase-frequency detection unit, and subsequently, a digitally controlled clock signal is produced.

REFERENCES:
patent: 5636192 (1997-06-01), Shimizume et al.
patent: 6052034 (2000-04-01), Wang et al.
patent: 6067071 (2000-05-01), Kotha et al.
patent: 6404247 (2002-06-01), Wang
patent: 6959064 (2005-10-01), Spijker et al.

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