Digital phase lock loop

Details Digital phase lock loop Digital phase lock loop

1999-03-18

2002-09-03

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S158000, C327S161000

Reexamination Certificate

active

06445229

ABSTRACT:

STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to electronic circuits and, more particularly, to digital phase lock loop circuits.
2. Description of the Related Art
In order to produce high frequency clocks, as required by many of today's VLSI (Very Large Scale Integration) circuits, integrated clock multipliers are used. Frequency multiplication can be produced by a number of different circuits. The most common of these circuits is the analog phase lock loop circuit (PLL).
The PLL suffers from many shortcomings. First, it cannot be digitally simulated, so verification of lock-up and jitter specifications is difficult. Secondly, PLLs require external components, which are not desirable in many applications.
Digital PLLs (DPLLs), on the other hand can be readily simulated and do not require external components. They offer other advantages, such as faster time-to-lock and they can maintain a lock output frequency even after loss of the reference signal. Once the reference signal is regained, a DPLL can remain in lock, unless there has been significant drift during loss of the signal.
Heretofore, however, many DPLL designs have had their own shortcomings. First, they may have excessive power requirements for many applications. Second, they may be unable to meet jitter requirements in some cases.
Therefore, a need has arisen for a low power DPLL able to meet strict jitter requirements.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a clock multiplier circuit. In a first aspect of the invention, circuitry for generating a series of clock cycles is provided, where each cycle has a logical high phase and a logical low phase, responsive to a transition of a reference clock signal. The generating circuitry comprises control circuitry coupled to a variable delay circuit for generating timing for both the logical high phases and logical low phases series of clock cycles.
This aspect of the invention provides for a single variable delay circuit for generating both high and low logical levels, thereby reducing circuitry and, hence, power requirements.
In a second aspect of the invention, a variable delay circuit is provided. A first delay circuit receives a control signal and outputs the control signal after a first controllable delay period. A second delay circuit receives the control signal and outputs the control signal after a second controllable delay period. A commutator coupled to the first and second delay circuits passes the output of the delay circuit with the shorter delay period.
This aspect of the invention provides a variable delay which can produce consistent incremental delays and does not use opposing amplifiers which can cause current spikes.
In a third aspect of the invention, a clock multiplier comprises circuitry for generating a series of clock cycles responsive to a reference clock, the length of the series of clock cycles dependent upon a controllable delay. Compare circuitry determines whether the length of the series of clock cycles exceeds the length of the reference clock. Circuitry for increasing the controllable delay operates responsive to said compare circuitry. Dividing circuitry divides the series of clock cycles to generate a divided clock signal after the controllable delay exceeds a predetermined delay.
This aspect of the invention automatically divides the series of clock cycles so that the clock multiplier can work over a broad frequency range.


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“Thèse de Doctorate de l'Universit{acute over (e )} Pierre et Marie Curie (Paris 6)”, Combes, MCG95: Générateur de Multiplier d'horloge, Dec. 12, 1994.

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