Digital phase lock loop

Details Digital phase lock loop Digital phase lock loop

1975-11-13

1976-09-28

Heyman, John S.

Oscillators

Relaxation oscillators

328134, 328 55, 328 72, 331 25, 329122, H03B 304

Patent

active

039834980

ABSTRACT:
A fast responding, low jitter, digital phase lock loop which is especially suited for synchronous, non return to zero, digitally encoded clock recovery applications.
Both leading and trailing transitions of the digital waveform triggers a monostable multivibrator which generates well defined transition pulses. These pulses are fed to a phase comparator, where they are simultaneously compared with the output of a programmable frequency divider, whose input couples to a reference frequency oscillator. The detected phase relationship between the two compared signals causes the divider to either increase, or decrease its division factor and thereby readjust the relative phase relationship between the divided signal and the digital signal until they are in phase lock.
During an absence of digital signal input, provision is made for selecting a third division factor whose value is between the first and second factors.

REFERENCES:
patent: 3209265 (1965-09-01), Baker et al.
patent: 3364439 (1968-01-01), Cohen et al.
patent: 3769602 (1973-10-01), Griswold
patent: 3789307 (1974-01-01), Clark
patent: 3936762 (1976-02-01), Cox et al.

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