Digital phase lock clock generator without local oscillator

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307262, 328155, 328 63, 328 72, 375119, H03K 513, H03K 522

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active

051736179

ABSTRACT:
A digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tapped output of the delay line goes through a two phase generator which in turn feeds back to the PD for comparison with the reference clock. This process is repeated until phase locking is obtained.

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patent: 4922141 (1990-05-01), Lofgren et al.
Design of PLL-Based Clock Generation Circuits, Apr. 1, 1987, Jeong, et al. 1987 IEEE, pp. 255-261.

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