Digital phase lock circuit

Details Digital phase lock circuit Digital phase lock circuit

1978-09-05

1980-12-30

Smith, Alfred E.

Boots, shoes, and leggings

328 25, 328 55, 364703, H03B 304, H03K 518

Patent

active

042426391

ABSTRACT:
A digital phase lock circuit wherein both the phase and frequency of an output signal are synchronized to an input signal. The present phase lock circuit is comprised of a clock signal source, first, second, and third counters, and a holding register. The first counter is utilized to count a predetermined number of cycles of the input signal to establish a first time period. The second counter receives as another input the clock signal and counts the clocks during the established first time period. The value of counted clocks contained in the second counter at the end of the first time period is divided by the predetermined number of cycles the first counter is set to count, and the result is stored in the holding register. The count in the holding register is used to preset the third counter which is then allowed to count down to zero, at the clock rate. The third counter is preset to the value contained in the holding register at each establishment of the first time period. The cycle time of the third counter is thus synchronized, in phase and frequency, to the incoming signal.

REFERENCES:
patent: 3006547 (1961-10-01), Fellows et al.
patent: 3646452 (1972-02-01), Horowitz et al.
patent: 3781695 (1973-12-01), Jackson
patent: 4143328 (1979-03-01), Kurita et al.

Affiliated with

Also associated with

Rating

Digital phase lock circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital phase lock circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital phase lock circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-9645