Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2000-06-26
2001-12-04
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S018000, C331S025000, C331S00100A, C327S156000, C327S159000
Reexamination Certificate
active
06326851
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to frequency synthesizers, and more particularly to an all-digital phase-domain phase-lock loop (PLL) frequency synthesizer that operates in a synchronous phase-domain to maximize a digitally-intensive architecture.
2. Description of the Prior Art
Frequency synthesizers using analog circuit techniques are well known in the art. Conventional RF frequency synthesizer architectures are analog-intensive and generally require a low loop bandwidth to reduce the familiar and well-known reference or compare frequency spurs. Low loop bandwidths are acceptable for RF-BiCMOS and RF-SiGe processes with weak digital capabilities.
Modern deep sub-micron CMOS processes and their RF-CMOS derivatives, however, are not very compatible with frequency synthesizer designs using analog circuit techniques. The conventional PLL-based frequency synthesizers generally comprise analog-intensive circuitry that does not work very well in a voltage-headroom-constrained aggressive CMOS environment. Such frequency synthesizers do not take advantage of recently developed high density digital gate technology.
Newer frequency synthesizer architectures have used sigma-delta modulated frequency divider techniques to randomize the above discussed frequency spurs by randomizing the spurious content at the cost of increased noise floor. These techniques have not significantly reduced the undesirable analog content. Other frequency synthesizer architectures have used direct digital synthesis (DDS) techniques that do not work at RF frequencies without a frequency conversion mechanism requiring an analog solution. Further, previous all-digital PLL architectures rely on an over-sampling clock. Such architectures cannot be used at RF frequencies.
In view of the foregoing, it is highly desirable to have a digitally-intensive frequency synthesizer architecture that is compatible with modern CMOS technology.
SUMMARY OF THE INVENTION
The present invention is directed to an all-digital phase-domain PLL frequency synthesizer that is compatible with deep sub-micron CMOS processes. The all-digital phase-domain PLL frequency synthesizer accommodates direct frequency/phase modulation transmission to remove the requirement for an additional transmitting modulator normally associated with wireless digital transmitters. This is accomplished by operating the PLL entirely in the phase-domain with maximum digital processing content such that the loop can be of high-bandwidth of “type 1” without the need for a loop filter. A “type 1” filter, as used herein, means a loop filter having only one integrating pole in the feedback loop. Only one integrating pole exists due to the VCO frequency-to-phase conversion. It is possible therefore, to eliminate a low-pass filter between the phase detector and the oscillator tuning input, resulting in a high bandwidth and fast response of the PLL loop.
According to one embodiment, the all-digital phase-domain PLL frequency synthesizer contains only one major analog component, a digitally-controlled 2.4 GHz voltage controlled oscillator (VCO or dVCO). The PLL loop is an all-digital phase-domain architecture whose purpose is to generate the 2.4 GHz high frequency f
osc
for the “BLUETOOTH” standard. The underlying frequency stability of the system is derived from a reference crystal oscillator, such as a 13 MHz TCXO for the global system for mobile communications (GSM) system. The phase of the VCO output is obtained by accumulating the number of significant (rising or falling) edge clock transitions. The phase of the reference oscillator is obtained by accumulating a frequency control word on every significant (rising or falling) edge of the reference oscillator output that is re-clocked via the VCO output. As used herein, “significant edge” means either a “rising” or a “falling” edge. A ceiling element continuously adjusts a reference phase value associated with the accumulated frequency control word by rounding off to the next integer (alternatively, truncating fractional bits necessary) to compensate for fractional-period delays caused by re-clocking of the reference oscillator by the VCO output. The phase error signal is then easily obtained by using a simple arithmetic subtraction of the VCO phase from the adjusted reference phase on every significant edge of the re-clocked reference oscillator output. The phase error signal can then be used as the tuning input to the digitally-controlled VCO directly via a gain element associated with the PLL loop operation.
In one aspect of the invention, an all-digital phase-domain PLL frequency synthesizer is provided that allows fast design turn-around using automated CAD tools.
In still another aspect of the invention, an all-digital phase-domain PLL frequency synthesizer is provided that achieves much less undesirable parameter variability than normally associated with analog circuits.
In yet another aspect of the invention, an all-digital phase-domain PLL frequency synthesizer is provided that allows ease of testability.
In yet another aspect of the invention, an all-digital phase-domain PLL frequency synthesizer is provided that requires desirably low silicon area to physically implement.
In yet another aspect of the invention, an all-digital phase-domain PLL frequency synthesizer is provided that requires lower power than conventional frequency synthesizers.
In still another aspect of the invention, an all-digital phase-domain PLL frequency synthesizer is provided that has direct frequency/phase modulation transmission capability to minimize system transmitter requirements.
In still another aspect of the invention, an all-digital phase-domain PLL frequency synthesizer is provided that accommodates the “BLUETOOTH” communication protocol.
REFERENCES:
patent: 5495205 (1996-02-01), Parker et al.
patent: 5546433 (1996-08-01), Tran et al.
patent: 5856761 (1999-01-01), Jokura
patent: 5910753 (1999-06-01), Bogdan
Leipold Dirk
Staszewski Robert B.
Brady III Wade James
Grimm Siegfried H.
Holmbo Dwight N.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Digital phase-domain PLL frequency synthesizer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital phase-domain PLL frequency synthesizer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital phase-domain PLL frequency synthesizer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2561255