Digital phase detector and phase-locked loop

Details Digital phase detector and phase-locked loop Digital phase detector and phase-locked loop

2011-06-21

2011-06-21

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S025000, C327S012000

Reexamination Certificate

active

07965143

ABSTRACT:
A digital phase detector is provided that can be easily implemented in gate array or FPGA, to accurately quantize a phase difference of two clocks and convert to a digital value without using delay elements. The digital phase detector includes: a multiplier for, when two clocks have frequencies close to an integer ratio, receiving a first clock and multiplying by M/N; F/F for latching a second clock by an output clock of the multiplier; a differential circuit for differentiating an output of the F/F; a counter for receiving the output clock of the multiplier; a latch circuit for holding an output of the counter according to an output of the differential circuit; a first adder for adding an output of the latch circuit; a second adder for subtracting an output of the first adder from a fixed value; and an accumulator for sequentially integrating an output of the second adder.

REFERENCES:
patent: 6429693 (2002-08-01), Staszewski et al.
patent: 7304510 (2007-12-01), Matsuta
patent: 7482880 (2009-01-01), Herrin et al.
patent: 7548123 (2009-06-01), Frey
patent: 2006/0214708 (2006-09-01), Huang et al.
patent: 2007/0008040 (2007-01-01), Mayer et al.
patent: 2002-076886 (2002-03-01), None
patent: 2007-110370 (2007-04-01), None

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