Digital phase detector

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307232, 328110, H03K 526

Patent

active

042374235

ABSTRACT:
A digital phase detector responsive to input signal transitions of first and second input signals for producing output current pulses of first and second polarities dependent upon whether the first input signal leads or lags the second; the width of the output pulses being proportional to the amount of phase lead or lag.
The phase detector includes two edge triggered bistable circuits for controlling a tri-state current source which provides positive, negative, or zero current depending upon the respective logical states of the bistable circuits. The detector circuit is arranged so that the bistable circuits are placed in the SET state by signal applied to their respective input terminals, provided both bistable circuits are in the RESET state. Each bistable circuit is RESET by pulses supplied from a respective pulse forming circuit. The pulse forming circuit is conditioned by the bistable circuit it drives to be selectively responsive to the input signal being applied to the other bistable circuit.
Only one of the bistable circuits is in the SET state at one time for the two input signals being out of phase. Both bistable circuits simultaneously alternate between SET and RESET states when the input signals are in phase.

REFERENCES:
patent: 3710140 (1973-01-01), Volmerange
patent: 3714463 (1973-01-01), Laune
patent: 4020422 (1977-04-01), Underhill
patent: 4027262 (1977-05-01), Sharpe
patent: 4122405 (1978-10-01), Tietz et al.
RCA COS/MOS Integrated Circuits-1977 "ICAN-6101" pp. 612-615-FIG. 3.

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